VLSI chip design and development Forum Index VLSI chip design and development
A forum to discuss all about VLSI chip design to be par in knowledge
 
 FAQFAQ   SearchSearch   MemberlistMemberlist   UsergroupsUsergroups    RegisterRegister 
 ProfileProfile   Log in to check your private messagesLog in to check your private messages   Log inLog in 

Welcome
Welcome to VLSI chip design and development.

You are currently viewing our boards as a guest, which gives you limited access to view most discussions and access our other features. By joining our free community, you will have access to post topics, communicate privately with other members (PM), respond to polls, upload content, and access many other special features. Registration is fast, simple, and absolutely free, so please, join our community today!

The time now is Fri Aug 29, 2008 4:51 am
VLSI chip design and development Forum Index		 View unanswered posts
 Forum   Topics   Posts   Last Post 
ASIC Design & Methodology  
No new posts
Verification Methodology
 A forum to discuss about Verification methodology, coverage Analysis/metrics, bus functional models, Testbench related issues
   
2 4 Mon Jun 16, 2008 7:59 am
gopi View latest post
No new posts
DFT and Test Issues
 A forum to discuss about Design for Test, BIST, BISR, Boundary Scan, Test pattern, Mechanism to reduce test patterns, At speed tests issues, Test challenges, Methods & Techniques to bring up coverage, Scan-chain,Wafer level burn in Tests, Shmoo plots,Known Good Dies....
   
1 4 Fri Jul 18, 2008 8:35 am
Ksd View latest post
No new posts
Modelling
 A platform to discuss about various Models involved in the Chip design flows ...
   
4 10 Sat Jun 07, 2008 10:07 pm
Lintrae View latest post
No new posts
Place & Route
 A platform to discuss about automatic place and route, tools, flows, methodologies involved in achieving timing closure...
   
9 19 Tue Jun 10, 2008 4:45 pm
chetanbs View latest post
No new posts
Architecture Design & RTL
 A platform to discuss about the various Architectural challenges.. Burning Technical issues and relevant architectural solutions, Design best practices, Technical Know hows, RTL challenges, Metastability issues , RTL for achieving best area/power/timing/dft issues...
   
1 1 Sat Jul 19, 2008 11:16 pm
dhishna View latest post
No new posts
Static Timing Analysis
 A forum to discuss about Static Timing Analysis, Constraints Definitions, Timing Models, Timing Checks, Timing Paths Analysis, Analysis Timing with Various uncertainities: Clock jitter/skews/process variations/on chip variations/IR drop...
   
7 17 Mon Nov 26, 2007 3:45 pm
vlsiasic View latest post
All times are GMT + 5.5 Hours
Who is Online
Who is Online Our users have posted a total of 55 articles
We have 124 registered users
The newest registered user is vlsikat
In total 8 user have visited this site today :: 0 Registered, 0 Hidden and 8 Guests , 3 of them within the last hour.
Registered Users: None
In total there is 1 user online :: 0 Registered, 0 Hidden and 1 Guest   [ Administrator ]   [ Moderator ]  
Most users ever online was 55 on Thu Jan 10, 2002 8:46 pm
Registered Users: None
This data is based on users active over the past five minutes
Log in
Username:    Password:      Log me on automatically each visit    

New posts New posts    No new posts No new posts    Forum is locked Forum is locked

Community Chest


Powered by phpBB
Hosted by FreeForums.org