VLSI chip design and development

Hi,

I am an electrical engineering student and I am doing the digital design of an 8-bit microcontroller in 90 nm as my graduation thesis using Design Compiler + SOC Encounter. I am having some problems trying to perform back-annotated synthesis, because I don´t really know in which step (after placement + trial routing, after placement + cts + routing,... ) should I extract the information and what to extract (sdf only, sdf + spef,....). I don't know either, how to specify in SOC Encounter that, after the first back-annotation, I´m using a resynthesised design.

I would be really grateful if somebody could give some information about the back annotated synthesis process, even if you are not using the same software, some explanation about the whole process will be really helpful to me (for example, how to deal with the clock tree in the back annotation process).

Thanks

Jose Moar