VLSI chip design and development

A forum to discuss all about VLSI chip design to be par in knowledge

Skip to content


Welcome
Welcome to <strong>VLSI chip design and development</strong>.

You are currently viewing our boards as a guest, which gives you limited access to view most discussions and access our other features. By joining our free community, you will have access to post topics, communicate privately with other members (PM), respond to polls, upload content, and access many other special features. Registration is fast, simple, and absolutely free, so please, <a href="/profile.php?mode=register">join our community today</a>!

clock low retention flip flops

A platform to discuss about the various Architectural challenges.. Burning Technical issues and relevant architectural solutions, Design best practices, Technical Know hows, RTL challenges, Metastability issues , RTL for achieving best area/power/timing/dft issues...
Post a reply

clock low retention flip flops

Postby ajith on Thu Oct 16, 2008 9:39 am

i want to know what is meant by clock low retention flip flops
ajith
 
Posts: 1
Joined: Wed Aug 27, 2008 6:11 pm
Top

Postby bhaskar on Mon Feb 09, 2009 5:56 am

HI
CLRFF are the flops which checks that the clock is low when the retention is asserted. If the condition fails the the flop will not retain the data and the behaviour of the flop is unprdictable or not as expected
bhaskar
 
Posts: 1
Joined: Mon Feb 09, 2009 5:50 am
Top
Post a reply

Return to Architecture Design & RTL

Who is online

Users browsing this forum: No registered users and 0 guests

Donate Now
Donate Now
Powered by phpBB © 2000, 2002, 2005, 2007 phpBB Group
Hosted by FreeForums.org | Create a free forum

cron