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D flip flop

A platform to discuss about various Models involved in the Chip design flows ...
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D flip flop

Postby rnithyacbe on Wed Mar 12, 2008 6:07 am

Hi, I am trying to design a positive edge triggered D flip flop using 0.13u CMOS technology.

I tried simulating dynamic and C2MOS flipflop's but got some wierd output. I get the correct output for a static D flopflop, but it has clock overlap problem.

Could anyone suggest which design would be the best?

Thanks in advance.
rnithyacbe
 
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Joined: Wed Mar 12, 2008 6:01 am
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