VLSI chip design and development

hi,

i have a setup violation in my design.
i dont know now what to do ... please suggest me i am in synthesis stage.

thanks ...

please respond fast

1. At first check whether the path is a valid path means whether this path will be exercised in your chip or it is a false path.
2. Check with the design specification whether the specified path could operate as a multicycle path rather than a single cycle path.

Assume it is a valid path.
1. Now check the wireload models used .
2. Check the loading of the high fanout nets.
3. group_path -from startpoint -to end point -weightage 100 and ask the tool to concentrate more on the specific paths.
4. use various compile options try with various switches.
5. Use designware components if you have logic similar to adders/multipliers .
6. Use compile_ultra options to speed up the paths which uses different algorithms for optimizations.
7. Use the flip-flops which has lesser setup time.
8. In case if the paths or of cross clock domains check whether the path is of synchronization logic, which usually is a false path as we have synchronizers in these paths.
9. In case you could use low Vt libraries which has faster delays can be used for specific paths to close on timing.check these options whether dual Vt flow is allowed .
10. check whether these paths could be solved in timing by using useful-skew concept after place and route by optimal clocktree building.

Praise the Lord.

hi all,
what i have to check in the wire load model,what happend if the load of the hfn nets is high how it related to setup violation.

group_path -from startpoint -to end point -weightage 100 and ask the tool to concentrate more on the specific paths.
explain in detail the above statement.

thanku

hi,

regarding high fanout nets(like resets, scan enables,scan mode signals), usually have high fanout nets.

To say to the synthesis tool as a HFN
you can either use

set_ideal_net <specify your hfn>

or

you can set it as false path through those nets(for time being to ignore those paths), you know these paths will meet timing and now the turn how to tell it to the tool the way it understands...

o.k. now regarding group_paths command...
usualy tool will be concentrating on the WNS(worst negative slack), so in order to concentrate the tool on the specific paths of our interest
group_path command will be really useful, wherein we will be giving the weightage for that path...

hope i answered...

Hi VLSICHIPDESIGNER,


I have one doubt,when we going to fix setup you had informed that first whether that path is valid path or not,i.e that path is false path or not.Here my doubt is before doing STA,SDC having false paths & multi cycle paths,then tool not going to do analysys for those paths.Again why we need to do check valid path.I am not understand this properly,please explain clearly.