It is currently Sun Nov 22, 2009 9:52 am
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Static Timing Analysis
A forum to discuss about Static Timing Analysis, Constraints Definitions, Timing Models, Timing Checks, Timing Paths Analysis, Analysis Timing with Various uncertainities: Clock jitter/skews/process variations/on chip variations/IR drop...
- 13 Topics
- 26 Posts
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Last post by ttnnqq02
Wed Sep 30, 2009 8:26 pm
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Verification Methodology
A forum to discuss about Verification methodology, coverage Analysis/metrics, bus functional models, Testbench related issues
- 4 Topics
- 6 Posts
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Last post by job2me02
Mon Sep 21, 2009 3:15 pm
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DFT and Test Issues
A forum to discuss about Design for Test, BIST, BISR, Boundary Scan, Test pattern, Mechanism to reduce test patterns, At speed tests issues, Test challenges, Methods & Techniques to bring up coverage, Scan-chain,Wafer level burn in Tests, Shmoo plots,Known Good Dies....
- 3 Topics
- 6 Posts
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Last post by job2me02
Mon Sep 21, 2009 3:14 pm
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Place & Route
A platform to discuss about automatic place and route, tools, flows, methodologies involved in achieving timing closure...
- 12 Topics
- 23 Posts
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Last post by job2me02
Mon Sep 21, 2009 3:14 pm
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Architecture Design & RTL
A platform to discuss about the various Architectural challenges.. Burning Technical issues and relevant architectural solutions, Design best practices, Technical Know hows, RTL challenges, Metastability issues , RTL for achieving best area/power/timing/dft issues...
- 6 Topics
- 7 Posts
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Last post by job2me02
Mon Sep 21, 2009 3:14 pm
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Modelling
A platform to discuss about various Models involved in the Chip design flows ...
- 5 Topics
- 11 Posts
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Last post by job2me02
Mon Sep 21, 2009 3:13 pm
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