VLSI chip design and development

A forum to discuss all about VLSI chip design to be par in knowledge

Skip to content


Welcome
Welcome to <strong>VLSI chip design and development</strong>.

You are currently viewing our boards as a guest, which gives you limited access to view most discussions and access our other features. By joining our free community, you will have access to post topics, communicate privately with other members (PM), respond to polls, upload content, and access many other special features. Registration is fast, simple, and absolutely free, so please, <a href="/profile.php?mode=register">join our community today</a>!

It is currently Sun Nov 22, 2009 9:52 am

  • Static Timing Analysis
    A forum to discuss about Static Timing Analysis, Constraints Definitions, Timing Models, Timing Checks, Timing Paths Analysis, Analysis Timing with Various uncertainities: Clock jitter/skews/process variations/on chip variations/IR drop...
    13 Topics
    26 Posts
    Last post by ttnnqq02 View the latest post
    Wed Sep 30, 2009 8:26 pm
  • Verification Methodology
    A forum to discuss about Verification methodology, coverage Analysis/metrics, bus functional models, Testbench related issues
    4 Topics
    6 Posts
    Last post by job2me02 View the latest post
    Mon Sep 21, 2009 3:15 pm
  • DFT and Test Issues
    A forum to discuss about Design for Test, BIST, BISR, Boundary Scan, Test pattern, Mechanism to reduce test patterns, At speed tests issues, Test challenges, Methods & Techniques to bring up coverage, Scan-chain,Wafer level burn in Tests, Shmoo plots,Known Good Dies....
    3 Topics
    6 Posts
    Last post by job2me02 View the latest post
    Mon Sep 21, 2009 3:14 pm
  • Place & Route
    A platform to discuss about automatic place and route, tools, flows, methodologies involved in achieving timing closure...
    12 Topics
    23 Posts
    Last post by job2me02 View the latest post
    Mon Sep 21, 2009 3:14 pm
  • Architecture Design & RTL
    A platform to discuss about the various Architectural challenges.. Burning Technical issues and relevant architectural solutions, Design best practices, Technical Know hows, RTL challenges, Metastability issues , RTL for achieving best area/power/timing/dft issues...
    6 Topics
    7 Posts
    Last post by job2me02 View the latest post
    Mon Sep 21, 2009 3:14 pm
  • Modelling
    A platform to discuss about various Models involved in the Chip design flows ...
    5 Topics
    11 Posts
    Last post by job2me02 View the latest post
    Mon Sep 21, 2009 3:13 pm

Login  •  Register

Who is online

In total there is 1 user online :: 0 registered, 0 hidden and 1 guest (based on users active over the past 5 minutes)
Most users ever online was 55 on Thu Jan 10, 2002 8:46 pm

Registered users: No registered users
Legend: Administrators, Global moderators

Statistics

Total posts 79 • Total topics 43 • Total members 139 • Our newest member vinayhs

Donate Now
Donate Now
Powered by phpBB © 2000, 2002, 2005, 2007 phpBB Group
Hosted by FreeForums.org | Create a free forum

cron