VLSI chip design and development Forum Index VLSI chip design and development
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The time now is Fri Aug 29, 2008 4:58 am
VLSI chip design and development Forum Index		 View unanswered posts
 Forum   Topics   Posts   Last Post 
ASIC Design & Methodology  
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Verification Methodology
 A forum to discuss about Verification methodology, coverage Analysis/metrics, bus functional models, Testbench related issues
   
2 4 Mon Jun 16, 2008 7:59 am
gopi View latest post
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DFT and Test Issues
 A forum to discuss about Design for Test, BIST, BISR, Boundary Scan, Test pattern, Mechanism to reduce test patterns, At speed tests issues, Test challenges, Methods & Techniques to bring up coverage, Scan-chain,Wafer level burn in Tests, Shmoo plots,Known Good Dies....
   
1 4 Fri Jul 18, 2008 8:35 am
Ksd View latest post
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Modelling
 A platform to discuss about various Models involved in the Chip design flows ...
   
4 10 Sat Jun 07, 2008 10:07 pm
Lintrae View latest post
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Place & Route
 A platform to discuss about automatic place and route, tools, flows, methodologies involved in achieving timing closure...
   
9 19 Tue Jun 10, 2008 4:45 pm
chetanbs View latest post
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Architecture Design & RTL
 A platform to discuss about the various Architectural challenges.. Burning Technical issues and relevant architectural solutions, Design best practices, Technical Know hows, RTL challenges, Metastability issues , RTL for achieving best area/power/timing/dft issues...
   
1 1 Sat Jul 19, 2008 11:16 pm
dhishna View latest post
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Static Timing Analysis
 A forum to discuss about Static Timing Analysis, Constraints Definitions, Timing Models, Timing Checks, Timing Paths Analysis, Analysis Timing with Various uncertainities: Clock jitter/skews/process variations/on chip variations/IR drop...
   
7 17 Mon Nov 26, 2007 3:45 pm
vlsiasic View latest post
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