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Muliple clock domain specification

A forum to discuss about Static Timing Analysis, Constraints Definitions, Timing Models, Timing Checks, Timing Paths Analysis, Analysis Timing with Various uncertainities: Clock jitter/skews/process variations/on chip variations/IR drop...
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Muliple clock domain specification

Postby goiko on Mon May 18, 2009 5:15 pm

Hello everybody,
I'm a student doing my master in hardware architectures. I have already designed a two clock domain system that works fine in a FPGA platform, but when I try to perform the timing analisis for an ASIC I get some confussing information.
For the FPGA version I set the time speciification and it runs correctly, both at the FPGA and at the post synthesys simulation.
But for the ASIC version I only now how to create the clock sources and I don't know how to specify the time requirements for the cross domain between the two clock domain. So i guess that the results I get are not reliable, at all.
I would be very happy, if anyone could help me.
Thanks a lot!!
goiko
 
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Joined: Mon May 18, 2009 5:03 pm
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