VLSI chip design and development

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what is the need for Dynamic simulation or gate level simul

A forum to discuss about Verification methodology, coverage Analysis/metrics, bus functional models, Testbench related issues
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what is the need for Dynamic simulation or gate level simul

Postby benjamin on Tue May 29, 2007 11:34 am

hi friends,

can you brief me on Dynamic simulation or gate level simulation and why it is needed.
benjamin
 
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Dynamic simulation is important in an VLSI chip design flow

Postby vlsichipdesigner on Mon Jun 04, 2007 11:17 am

Dynamic Simulation importance.
1. In case if we had made some mistakes in constraining the chip say by mistake we had added some false and multicycle paths, then it would be got verified only by Dynamic simulations.
2. In order to know whether the chip comes out of Reset or not, only Dynamic simulation can guarantee...

hope this answers

Praise the Lord

vlsichipdesigner
www.vlsichipdesign.com
vlsichipdesigner
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