VLSI chip design and development

hi,

i have a question how to verify that my clock is coming correctly incase of a gated clock. or how do i make sure that glitches or there in a clock gating. Is there any way i can check in STA.

thanks,

you are correct, clock gating checks are important, otherwise possibility of design getting in to a glitch is more.

There is a clockgating check you turn the variable to on and enable the tooll to verify the clock gating logic.

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