VLSI chip design and development

what is SPEF format mean and why is it needed and in which part of the flow it is used ?

SPEF file stands for Standard Parasitics Exchange format .
1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System.

SPEF file has the parasitics information (Resistance,capacitance and inductance ) values for the chip. The extraction tool used in the market is StarRC (synopsys company).

This format is used for as the delay information(for cell and the wires), and this file is used for Static timing analysis to qualify timing after place and route.

Hope this is clear...

How different is SDF from SPEF?

hi,

SDF stands for Standard Delay Format
SPEF stands for Standard Parasitics Exchange Format.

In the SDF you can see the real delay numbers.
whereas in the SPEF file the delay numbers will be interms of Resistance, capacitance numbers and the tool which reads the SPEF file need to compute the delay calculation based on the Resistance & capacitance network....

So is that means SDF is calculated SPEF? I saw back-end guys use spef while front end use sdf.

hi,

yes you are correct...
If SDF is derived from SPEF file then the SDF will have the wire delay also ,in case if SDF is derived from pre-routed database then the SDF will have only the cell delay.

usually the flow is ...

1. perform synthesis
2. Perform place & route activities.
3. Extract the database (RC extraction)
4. read the routed verilog netlist and extracted SPEF from the extractor in the delay calculation tool(could be primetime).. and dump an SDF.
5. use this SDF file for the dynamic simulations, and run the test vector's.