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CTS

 
Post new topic   Reply to topic    VLSI chip design and development Forum Index -> Static Timing Analysis
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lokesh_boddu



Joined: 26 Jun 2007
Posts: 1

PostPosted: Thu Sep 06, 2007 9:51 am    Post subject: CTS Reply with quote

Hi

wht is pre CTS and Post CTS,wht is the use of CTS in STA

wht is clock jitter,clock skew,margin

Regards
Lokesh
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vlsiasic



Joined: 26 Nov 2007
Posts: 4

PostPosted: Mon Nov 26, 2007 3:45 pm    Post subject: Reply with quote

CTS is a step where in your tool builds in the actual clock tree and routes them to the respective clock pins....
In the preCTS stage the tool takes in the constraints specified by the user(latency values,skew values) and generates the timing reports....its the ideal one
In the postCTS the tool generates the timing analysis report based on the clock tree which has been built up during CTS... its the actual computed mode.......

Clock jitter is the amount of cycle-to-cycle variation that can occur in a clock s period.
Clock skew is the difference in the latest ans earliest arrival time of the clock.
Margin is the
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