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	VLSI chip design and development Forum Index -> Static Timing Analysis	Mark all topics read

Topics		Replies	Author	Views	Last Post
	CTS	1	lokesh_boddu	539	Mon Nov 26, 2007 3:45 pm vlsiasic
	hold violation affects data rate?	0	vlsiasic	352	Mon Nov 26, 2007 3:29 pm vlsiasic
	i have a setup violation ? now what should i do?	3	augustin	751	Fri Aug 03, 2007 4:57 am vlsichipdesigner
	Is there any way to check clock-gating in STA	1	augustin	529	Mon Jun 11, 2007 4:19 pm vlsichipdesigner
	can i specify all the paths as multicycle paths	1	augustin	467	Mon Jun 11, 2007 4:17 pm vlsichipdesigner
	can you briefly explain me what is false path	2	augustin	616	Mon Jun 11, 2007 4:12 pm vlsichipdesigner
	what are the various timing paths to be verified in STA	2	augustin	642	Wed Jun 06, 2007 5:18 pm vlsichipdesigner
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