asic gate level netlist simulation
Posted: Thu Feb 19, 2009 2:33 pmHello sir ,
I am a student, doing my masters in vlsi. Currently i am working on my final year project, and i have some problem in gate level netlist simulation(simulation tool VCS). My RTL code simulation is working fine but gate level simulation is not working(getting XXX state). But the design successfully passes the formal verification. Please give me some solution.
I am a student, doing my masters in vlsi. Currently i am working on my final year project, and i have some problem in gate level netlist simulation(simulation tool VCS). My RTL code simulation is working fine but gate level simulation is not working(getting XXX state). But the design successfully passes the formal verification. Please give me some solution.