VLSI chip design and development

hi ,

i here a lot of the term called as SDC file, what does this mean, and why it is needed and which part of the flow it is required.

thanks,
laxmi

SDC is synopsys desigfn constraints .
It is a standard format which is understood by several EDA tool vendors such as MAGMA and tools like spyglass etc.
This file is typically used to mention the timng constraints such as input/output delays, false paths , multicycle paths etc.
THis can be generated through Primtime and can be used as an input for timing optimization for other tools.